VL25 输入序列连续的序列检测
这种题用移位寄存器是最方便的，用状态机会麻烦很多。
`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [7:0]seq; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin seq <= 0; match <= 0; end else begin seq <= {seq[6:0],a}; if(seq == 8'b01110001) match <= 1; else match <= 0; end end endmodule
VL26 含有无关项的序列检测
和上一题一样用移位寄存器即可。
`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0]seq; always@(posedge clk or rst_n) begin if(~rst_n)begin seq <= 0; match <= 0; end else begin seq <= {seq[7:0],a}; if(seq[8:6]==3'b011&&seq[2:0]==3'b110) match <= 1; else match <= 0; end end endmodule
VL27 不重叠序列检测
要求使用状态机实现，我这里使用了一个标志位flag进行判断，只要有不匹配的情况就代表没有检测到序列，省去了麻烦的状态跳转，六个状态顺序执行。
`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); localparam S0=0,S1=1,S2=2,S3=3,S4=4,S5=5; reg [2:0]state,next_state; reg flag; always@(posedge clk or negedge rst_n) begin if(~rst_n) state <= S0; else state <= next_state; end always@(*) begin case(state) S0:next_state=S1; S1:next_state=S2; S2:next_state=S3; S3:next_state=S4; S4:next_state=S5; S5:next_state=S0; default:next_state=S0; endcase end always@(posedge clk or negedge rst_n) begin if(~rst_n)begin flag <= 0; match <= 0; not_match <= 0; end else begin case(state) S0:begin flag <= data?1:flag; match <= 0; not_match <= 0; end S1:flag <= data?flag:1; S2:flag <= data?flag:1; S3:flag <= data?flag:1; S4:flag <= data?1:flag; S5:begin flag <= 0; if(flag||data)not_match <= 1; else match <= 1; end endcase end end endmodule
VL28 输入序列不连续的序列检测
同样是要求使用状态机实现，只在data_valid时判断并跳状态即可。
`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); localparam S0=0,S1=1,S2=2,S3=3; reg [1:0]state,next_state; always@(posedge clk or negedge rst_n) begin if(~rst_n) state <= S0; else state <= next_state; end always@(*) begin case(state) S0:begin if(data_valid) next_state = data ? S0 : S1; else next_state = S0; end S1:begin if(data_valid) next_state = data ? S2 : S1; else next_state = S1; end S2:begin if(data_valid) next_state = data ? S3 : S0; else next_state = S2; end S3:begin if(data_valid) next_state = data ? S0 : S1; else next_state = S3; end endcase end always@(posedge clk or negedge rst_n) begin if(~rst_n) match <= 0; else begin if(state == S3 && data == 0) match <= 1; else match <= 0; end end endmodule
VL29 信号发生器
很垃圾的一道题，信息都不全，波形又看不清，难度其实不大。
`timescale 1ns/1ns module signal_generator( input clk, input rst_n, input [1:0] wave_choise, output reg [4:0]wave ); reg [5:0]counter; reg up; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin wave <= 0; counter <= 0; up <= 0; end else begin case(wave_choise) 0:begin counter <= (counter<19)?counter + 1:0; if(counter==19) wave <= 0; else if(counter==9) wave <= 20; end 1:begin wave <= (wave<20)?wave + 1:0; end 2:begin wave <= up?wave+1:wave-1; if(wave == 20)begin wave <= wave -1; up <= 0; end else if(wave == 0)begin wave <= wave + 1; up <= 1; end end endcase end end endmodule
VL30 数据串转并电路
注意时序输出延后一个周期，所以为了时序和题目保持一致，输出时应该输出{data_a,data[5:1]};
`timescale 1ns/1ns module s_to_p( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , output reg valid_b , output reg [5:0] data_b ); reg [2:0]count; reg [5:0]data; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin ready_a <= 0; valid_b <= 0; data_b <= 0; data <= 0; count <= 0; end else begin ready_a <= 1; if(valid_a&&ready_a)begin count <= (count<5)?(count +1):0; data <= {data_a,data[5:1]}; end if(count == 5)begin valid_b <= 1; data_b <= {data_a,data[5:1]}; end else valid_b <= 0; end end endmodule
VL31 数据累加输出
注意以下输出后把data_out清空。
`timescale 1ns/1ns module valid_ready( input clk , input rst_n , input [7:0] data_in , input valid_a , input ready_b , output ready_a , output reg valid_b , output reg [9:0] data_out ); reg [1:0]count; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin count <= 0; data_out <= 0; valid_b <= 0; end else begin if(valid_a&&ready_a)begin if(count == 0)begin count <= count + 1; valid_b <= 0; data_out <= data_in; end else if(count < 3)begin count <= count + 1; data_out <= data_out + data_in; end else begin valid_b <= 1; count <= 0; data_out <= data_out + data_in; end end end end assign ready_a = (~valid_b)||ready_b; endmodule
VL32 非整数倍数据位宽转换24to128
这道题有点难度，一开始想岔了，以为只要输入六个24位数据，舍弃最后16位，看题解发现最后16位要作为下一个128位数据的开头，晕。
128*3/24=16，所以16个周期为一次循环。
`timescale 1ns/1ns module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg valid_out , output reg [127:0] data_out ); reg [3:0]count; always@(posedge clk or negedge rst_n) begin if(~rst_n) count <= 0; else if(valid_in) count <= count + 1; end always@(posedge clk or negedge rst_n) begin if(~rst_n) valid_out <= 0; else begin if(count==5||count==10||count==15) valid_out <= 1; else valid_out <= 0; end end reg [127:0]temp; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin data_out <= 0; temp <= 0; end else if(valid_in)begin temp <= {temp[103:0],data_in}; if(count == 5) data_out <= {temp[119:0],data_in[23:16]}; else if(count == 10) data_out <= {temp[111:0],data_in[23:8]}; else if(count == 15) data_out <= {temp[103:0],data_in}; end end endmodule
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